VLSI implemented ML joint carrier phase and timing offsets estimator for QPSK/OQPSK burst modems
Baras, John, S.
Date: September 21 - September 24, 1999
A high-performance ASIC supporting multiple modulation, error correction, and frame formats is under development at Hughes Network Systems, Inc. Powerful and generic data-aided (DA) estimators are needed to accommodate operation in the required modes. A simplified DA maximum likelihood (ML) joint estimator for carrier phase and symbol timing offset for QPSK/OQPSK burst modems and a sample systolic VLSI implementation for the estimator are presented. Furthermore, the Cramer-Rao lower bound (CRLB) for DA case is investigated. The performance of the estimator is shown through simulation to meet the CRLB even at low signal-to-noise ratios (SNR). Compared with theoretical solutions, the proposed estimator is less computationally intensive and is, therefore, easier to implement using current VLSI technology